What to Fix First When GaN FET Gate Oscillation Trashes Frame Pacing

You're chasing a stutter that shows up every few seconds — frame window variance that spikes like clockwork. You've swapped drivers, reinstalled the OS, even tried different RAM kits. Nothing sticks. Then you put a scope on the GaN FET gate, and there it's: a 200 MHz ring that decays for half a microsecond after every switching edge. That wobble is coupling into the 12V rail, and the GPU's voltage regulator is fighting back. Welcome to the real reason your frame pacing looks like a seismograph during an earthquake.

Gate oscillation in GaN FETs isn't new, but in gaming hardware — where every millisecond of stable voltage matters — it's a hidden wrecking ball. This article walks you through the fix batch that actually works, based on bench work with high-current GPU VRMs and overclocking check rigs. No theory for theory's sake. Just what to reach for primary, second, and third.

Where GaN Gate Oscillation Shows Up in Real Work

GPU VRM Stage Ringing Visible on Scope

Plug a near-site probe into your 500 MHz scope, hover it over the GaN FETs feeding a high-end GPU — what you see is rarely clean. I have watched a 48 MHz ring ride the gate voltage on an RTX 4090-equivalent VRM stage, right when the core pulled 400 A transient. That ringing is not a benign overshoot gimmick. It modulates the FET’s on-resistance in the tens‑of‑nanoseconds window. rapid reality check — one cycle of that ring and the inductor current sloshes differently. The next frame has 12 μJ less energy in the bulk cap. You lose a frame open. The catch is that most builders probe only the output rail and call it done. They miss the gate node entirely.

The pattern repeats: a 25 ns oscillation on the gate pin, visible between the driver output and the FET’s Kelvin source. Miller plateau regions get distorted. Shoot‑through current spikes follow. That looks like a driver‑sizing snag, but it’s actually a resonant tank formed by the gate loop inductance and the FET’s input capacitance. off fix if you swap the driver initial — you just move the resonant frequency. We fixed this by adding a 2.2 Ω gate resistor in series and a ferrite bead on the bootstrap supply. Oscillation dropped from 1.8 Vpp to 0.3 Vpp. Frame‑slot jitter fell by half.

Frame slot Variance Correlated with Switching Events

Run a frame‑pacing histogram alongside a slot‑correlated current probe on the 12 VHPWR cable. Most crews skip this: solder a BNC pigtail to the VRM input and trigger on the switching edge. The correlation is nasty — every heavy load transient in the GPU VRM produces a 0.7–1.2 ms spike in frame delivery slot. That's not a random CPU scheduling glitch; the P‑state controller hiccups when the gate ring pushes the feedback loop into subharmonic instability. The frame pacing chart shows a comb‑tooth pattern: stable for four frames, then one frame delivered 3 ms late. Rinse, repeat.

“We chased a frame‑phase variance ghost for six weeks. Turned out to be 8 mm of extra gate‑loop trace length on the secondary side. Cut it, oscillation dropped, frame pacing flattened.”

— Lead hardware engineer, GPU‑module group, 2024 project post‑mortem

The trade‑off is painful — to see the correlation you need a scope with enough memory depth to capture 16 000+ switching cycles per frame. That's a 4‑channel, 12‑bit rearm at 1 GS/s. Not everyone has one. But without that capture, you will swap VRM caps, change switching frequency, and still see the same comb‑tooth pacing. We learned to trigger on the falling edge of the low‑side gate signal; that edge is where the resonant energy dumps back into the driver. Every window the gate ring exceeds 0.5 V, the next frame’s completion timestamp shifts by 80–120 μs. That hurts.

Common check Setups That Reveal the snag

Three setups expose gate oscillation reliably — and none use a gaming‑benchmark overlay. initial: DC‑DC eval board with the same GaN FET and driver as the target GPU, running a pulsed current load at 20 A/μs slew. If the gate rings at >40 MHz under that edge, it will ring in‑system. Second: in‑circuit with a 10 pF scope probe (no ground lead, use a spring tip) on the gate node during a synthetic load phase generated by a fast‑switch e‑load. Third: near‑floor H‑site loop over the driver‑to‑FET trace, while the GPU runs a frame‑spike workload like a shader‑intensive scene change. The H‑floor plot shows exactly where the energy radiates.

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The pitfall: using a 10× passive probe with a long ground clip. That probe adds 15 nH of ground inductance and dampens the real oscillation. You see a clean waveform and think “no snag here.” off reading. The actual gate ring is 2× worse. Use an active FET probe or a 50 Ω coaxial feedthrough — that's the only way to trust the measurement. What usually breaks initial is the builder’s assumption that the scope picture is the final truth. It's not. A false‑clean trace delays the fix by two weeks and overheads a respin. I have seen that happen three times this year alone.

Foundations Readers Confuse: Gate Ring vs. Power Integrity

Gate Ring vs. Output Ripple — The Mix-Up That expenses Hours

The easiest trap: you see a squiggly voltage trace on the drain, blame power delivery, and swap bulk caps. I have watched groups burn two days replacing VRM output capacitors when the real culprit was a 120 MHz GaN gate oscillation. Gate ringing lives in the switch-node loop — the tiny high‑dI/dt path between FET, driver, and decoupling. Output ripple lives in the load-side filter. Two different domains. One fix kills the off issue. What usually breaks opening is the assumption that low‑frequency ripple (3 µV at 200 kHz) and high‑frequency ringing (20 Vpk‑pk at 200 MHz) behave the same way. They don't. Ripple couples through output capacitance; ringing couples through the gate‑drain parasitic Cgd and the driver's return inductance. Same board, different physics.

Why Ringing Doesn't Always Cause Visible Stutter

You can have 15 V of gate ringing and zero dropped frames — if the ringing decays before the next PWM cycle. The catch is: GaN's threshold voltage sits around 1.2 V. A 4‑ns overshoot that crosses that threshold does cause unintended partial turn‑on. That partial event steals a few hundred picoseconds from the dead slot. No stutter yet. But the next cycle arrives with the output node in a slightly different pre‑charge state, the inductor current ramps asymmetrically, and the frame‑pacing timing controller sees a 2‑µs jitter in the voltage‑regulation error. That jitter is the stutter. It doesn't show up as a dropped frame — it shows up as micro‑hitches that feel like network lag but are purely electrical. I have debugged exactly this: a 35‑mm GPU riser cable added 3 nH of extra gate‑source loop, raised the ringing frequency from 185 MHz to 205 MHz, and introduced a 1.6‑µs pacing creep. A 2‑mm ferrite bead on the gate resistor fixed it. The output caps were fine all along.

“We swapped the VRM twice before someone looked at the gate drive waveform. primary fix was a 1‑Ω series gate resistor. Second fix was moving the driver 3 mm closer.”

— bench engineer, GPU validation lab, after a 14‑day debugging cycle

The Role of Dead slot and Cross‑Conduction

Ringing doesn't just cause overshoot — it eats dead window asymmetrically. When the low‑side GaN's gate oscillates during the dead‑window window, the high‑side FET sees a false turn‑on signal through the bootstrap diode's reverse recovery. That creates a shoot‑through event that lasts maybe 500 ps. One shot.

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Now repeat that at 2 MHz switching frequency. The cross‑conduction energy accumulates, the junction temperature rises 8–12 °C, and the on‑resistance drifts. Higher RDS(on) shifts the regulator's load‑line — and the frame‑pacing budget collapses because the output voltage droops an extra 5 mV during a 20‑A transient. The fix queue matters: fix the gate ringing before you touch the dead‑window register. Why? Because a clean gate waveform reveals the true dead‑window margin. Dead‑slot tweaks on a ringing gate are like tuning a guitar with a warped neck — you can get it close, but the next temperature cycle undoes everything. I have seen units revert dead‑slot adjustments three times before admitting the root cause was a 6‑mm trace that should have been 2 mm. flawed queue. That hurts.

Patterns That Usually Work: Fix queue That Sticks

opening phase: reduce gate drive strength

Most crews reach for a bigger driver when they see oscillation. faulty transition. The gate driver's output impedance and slew rate directly shape the energy dumped into the GaN FET's parasitic capacitance. I have seen a 2Ω increase in driver impedance kill a 120 MHz ring that four layout spins failed to fix. Drop the drive current from 4 A to 2 A primary. Measure the gate-voltage waveform at the FET body — not at the driver output. The distance between those two points hides a transmission-line reflection that amplifies the ring. Lose the overshoot before you add components.

The catch is that weaker drive slows the switching edge. You might trade 2–3 ns rise slot for clean turn-on. That sounds fine until the dead-slot window shrinks and shoot-through appears. Monitor the half-bridge midpoint voltage during the initial 10 ns after each transition. If you see a voltage blip that crosses the threshold, back off the drive reduction and try the next move instead. One variable at a phase. No shotgun changes.

Second stage: add a series gate resistor

A 10 Ω carbon-film resistor placed within 5 mm of the GaN gate pin damps the LC tank formed by the gate inductance and input capacitance. We fixed a 200 W server PSU by swapping a 0 Ω jumper for 15 Ω — noise dropped 18 dB at 80 MHz. But the resistor also creates a voltage divider with the gate-driver output impedance. rapid reality check: a 10 Ω resistor with a 2 V gate-drive swing adds roughly 0.3 V of drop under charging current. That hurts threshold margin on GaN parts with Vth around 1.2 V. Verify the plateau voltage at full load before you commit.

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Use a lone resistor per gate — not a network. Multiple parallel resistors increase parasitic capacitance and shift the resonance up in frequency. I watched a staff chase a 150 MHz oscillation for three days because they used two 22 Ω resistors in parallel. One 10 Ω part eliminated the ring in one prototype iteration. Should you use a resistor above 22 Ω? Rarely. The turn-off energy climbs and the Miller plateau stretches, which eats into efficiency. Stay between 4.7 Ω and 15 Ω unless your loop inductance is extreme.

We swapped a zero-ohm jumper for 15 Ω and the 80 MHz spur vanished. Two days of scoping, twenty cents of parts.

— Power engineer, high-frequency DC-DC module project

Third stage: snubber across drain-source

A 100 pF capacitor in series with 1 Ω placed directly across the drain and source terminals absorbs the energy that the gate fix can't reach. This is not a band-aid — it's the correct termination for the parasitic capacitance that remains after steps one and two. The snubber's RC window constant should match half the oscillation period. Example: a 70 MHz ring needs a slot constant near 7 ns. A 100 pF cap and 1 Ω resistor give 0.1 ns — too fast. Increase the capacitor to 470 pF and the resistor to 2.2 Ω. That yields roughly 1 ns. Iterate until the ring amplitude drops below 5% of the drain-source voltage.

The trade-off is hard switching loss at every transition. Every picojoule stored in the snubber capacitor gets dissipated each cycle. At 1 MHz with 470 pF and 50 V drain swing, that's about 1.2 W of extra heat. Acceptable for a 300 W stage. Not acceptable for a laptop charger. Measure the temperature rise of the snubber resistor after ten minutes of full load — if it exceeds 60 °C, reduce the capacitance or move to a ferrite-based solution.

Fourth phase: ferrite bead on gate path

If the oscillation persists after three steps, place a ferrite bead with 100 Ω impedance at 100 MHz between the series resistor and the gate pin. This absorbs high-frequency energy without increasing DC resistance. The bead adds approximately 2 nH of series inductance — watch for resonance with the gate capacitance. check with a network analyzer if possible; otherwise, probe the gate waveform at turn-on and turn-off. A bead that rings with the driver's output capacitance creates a new oscillation at a different frequency. Not a fix, just a relocation.

I have seen groups stack two beads in series thinking more is better. That creates a low-Q resonant tank that amplifies noise near 200 MHz. One bead, one resistor, one clean layout. The sequence matters — skipping straight to a bead without reducing drive strength initial masks the root cause. The underlying high dV/dt still stress the GaN's gate oxide. Frame pacing looks stable for an hour, then the seam blows out under thermal creep. begin at stage one. Iterate forward. Don't jump. Your oscilloscope's FFT will thank you.

Anti-Patterns and Why crews Revert

Slapping on a Larger Resistor Than Needed

Bigger must be better for damping, right? off. I have watched units throw a 10 Ω gate resistor at a 1 Ω issue and call it done. The oscillation quiets down — temporarily — but the switching edge turns into a wet noodle. That soft edge kills dead-slot margins, cross-conduction creeps in, and frame pacing turns into a stuttery mess because the GaN FET never fully saturates before the next cycle hits. The catch is that most oscilloscope probes miss the real waveform at the die because probe ground inductance masks the true ringing amplitude. So the engineer sees a clean gate trace, declares victory, and ships a board that fails in the primary thermal soak check.

What usually breaks initial is the bootstrap capacitor — it takes a voltage spike from the slowed Miller plateau and lets the magic smoke out. One concrete anecdote: a customer's 800 W PSU design showed perfect gate edges on the bench but hit 50 °C on the driver after ten minutes. We measured the actual FET turn-off window and found it had stretched from 12 ns to 38 ns. The extra gate resistance? That was the culprit. They reverted to 2.2 Ω and fixed the layout instead. Smaller resistor, better pacing.

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'The group spent three weeks trying to program around a frame-window jitter that was actually a 4 Ω resistor hiding in plain sight.'

— lead power engineer, after ripping out all 'safety margin' gate resistors

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Adding Capacitance Without Calculating Resonance

An extra 100 pF across the gate-source sounds like a cheap fix. It's — until you do the math. That cap interacts with the gate-driver output impedance and the PCB trace inductance to form a new LC tank, often right inside the switching frequency band. Now you have oscillation at 80 MHz that was not there before, and it injects common-mode noise straight into the feedback loop. The GPU frame buffer starts reporting random completion times; the game looks smooth on a 60 Hz monitor but micro-stutters on a 144 Hz panel.

Most crews skip this: they never sweep the impedance profile of the gate loop before soldering extra components. The result is a board that passes benchtop tests at room temperature but fails in a 40 °C chamber because the resonance shifts with temperature. Adding capacitance without calculating the Q factor is like stuffing insulation into a chimney — it might block the draft, but the smoke goes somewhere else. Reverting the cap and re-routing the gate return trace usually restores proper frame pacing within one board spin. That hurts, because it means throwing away the 'easy' fix and doing the hard layout work.

Ignoring Layout Parasitics and Blaming the FET

Here is the classic pattern: a crew sees gate ringing, swaps the GaN FET for a different lot or a different part number, and nothing improves. Then they blame the device. faulty order. The real issue is almost always a 5 mm trace from the driver to the FET gate paired with a return path that loops through three vias and a ground plane split. That stub inductance resonates with the FET's input capacitance at frequencies well above 100 MHz—far beyond what most lab scopes capture with a 10 cm ground lead.

I have seen engineers change FETs four times, redesign the thermal pad, and even swap the controller IC before someone thought to lift the gate trace and add a Kelvin-source connection. The frame-pacing jitter vanished. The fix was free — just copper and attention to loop area. Why do crews revert to blaming the FET? Because re-spinning a PCB overheads a week and a few thousand dollars, but re-spinning a BoM spend nothing on paper. That's a trap. The layout fix often means delaying a product launch, and project managers hate that. So the band-aid resistor goes back in, the oscillation stays under the noise floor on paper, and the gamer at home gets random 15 ms frame pauses they can't reproduce on a check bench. Not acceptable.

fast reality check—a tight gate loop with a dedicated source return trace eliminates 80 % of oscillation problems before any component value changes. The remaining 20 % need careful RC damping, not shotgun capacitor additions. Next window you see gate wobble, measure the physical trace length primary. Then decide.

Maintenance, slippage, and Long-Term spend

Temperature sensitivity of GaN gate threshold

The fix that worked at 25°C can fall apart at 60°C. GaN FETs have a notoriously shallow gate threshold—often 1.2 V to 1.6 V—and that number drifts with junction temperature. I have watched a carefully tuned gate resistor network turn into a ringing mess after twenty minutes of sustained gaming. The die heats up, Vth drops a few hundred millivolts, and suddenly the gate driver is fighting oscillation it never saw on the bench. That hurts. Most groups cool the board with a desk fan during debug and never check at thermal equilibrium. Real result: frame pacing looks clean for the initial match, then stutters appear thirty minutes in. The fix? Characterize gate-drive timing at three temperature points—idle, load, and sustained load—before calling the layout done.

Aging effects on gate resistance

Gate resistors burn in. Not dramatically, but they wander—especially thin-film types pushed near their rated power. A 10 Ω gate resistor that held oscillation at bay for a year can climb to 11.5 Ω after 10,000 thermal cycles. That extra ohmic shift changes the damping factor. I have seen a system that passed qualification fail in the site six months later, and the only difference was resistor aging. The catch is subtle: most failure-analysis labs look for short circuits, not a 15 % resistance increase on a lone 0402 part. We fixed one by replacing all critical gate resistors with metal-film types rated for 2× the peak dissipation. Should have done that on rev A.

When snubbers burn up and need replacement

RC snubbers across the drain-source node are the standard band-aid for GaN gate oscillation. They work—until they don't. The capacitor self-heats from ripple current, the dielectric ages, and the ESR rises. Once ESR climbs, the snubber becomes less effective at the exact oscillation frequency it was meant to kill. Frame pacing degrades slowly, not in a solo crash. Players notice micro-stutters that are hard to reproduce. Most units revert the snubber fix entirely, blaming the layout or the FET model. Our repair logs showed a different pattern: snubber capacitors failed open or high-ESR in about 12 % of units after 18 months. Replacement with C0G/NP0 dielectrics eliminated the creep. fast reality check—ceramic class 2 caps (X7R, X5R) age faster than most engineers remember.

'The oscillation didn't come back. What came back was the aging of the part that killed it.'

— bench-repair lead, during a post-mortem on a failed batch of high-refresh monitors

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Maintenance for GaN oscillation fixes is not optional. Plan for temperature drift, resistor aging, and snubber decay before the initial production run. That means testing at temperature, specifying long-life passives, and budgeting for one re-spin after the initial bench data comes in. Skip this, and your frame pacing will get worse with window—not better.

When Not to Use This Approach

When oscillation is below 50 MHz and doesn't affect load regulation

Not every ringing trace kills frametime consistency. I have spent three days chasing a 38 MHz gate wiggle that looked awful on the scope—clean sine, ~400 mV peak-to-peak—and then null-checked it by swapping the GaN FET for a Si part with identical package. The frame pacing chart didn't shift. Zero difference. That hurts. The catch is: low-frequency oscillation often couples into the feedback node only if the load transient is mild or the output capacitance is oversized. If your Vcore droop stays under 15 mV during a 40 A phase, that sub-50 MHz ring is scenery, not a saboteur. Fix the actual power-stage stability opening. Most crews skip this: they tune the gate resistor until the ring is flat, then wonder why the 120 Hz input ripple still tears the frame sequence apart. faulty order.

rapid reality check—open the loop-gain plot. If the phase margin at the switching frequency crosses 60°, chasing gate oscillation is a waste of solder slot. The real frame stutter comes from the bulk capacitor bank aging or a missing ceramic bypass at the load point. We fixed a high-end GPU backplate once where the customer swore the GaN gate was oscillating. Fifty-six decibels of gain margin later, the root cause was a 22 µF MLCC that had cracked during reflow. The gate ring was a ghost. Not every shimmer in the waveform is a demon—sometimes it's just a shadow.

When the real snag is input capacitance ripple

Input capacitance ripple is the silent frame killer that gate-oscillation hunters ignore. The GaN gate looks pristine—clean turn-on, zero overshoot—but the input voltage sags 200 mV at the beat frequency of the game's draw-call burst. That sag propagates through the duty-cycle correction loop and lands as a micro-stutter every 16 ms. You tune the gate resistance for three hours and the stutter stays. Why? Because the gate oscillation was never the villain; the input rail was collapsing under its own ESR. The fix is bulk electrolytics on the 12 V rail, not snubber components at the switch node.

That said, pouring capacitance into the input is a bandage if the layout forces long return paths. I have seen a design where the input capacitors sat 18 mm from the GaN drain—too far. The parasitic inductance created a 70 MHz tank that looked like gate oscillation but was actually a resonance between the input loop and the output filter. Scope probe at the gate showed a sin wave; scope probe at the input bulk showed the exact same frequency, inverted. The group had already ordered 0805 snubber parts. They reverted. —field note from a 2023 VR headset teardown

—role: input-loop resonance misidentified as GaN gate oscillation in a space-constrained product

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When you're stuck with a fixed layout and no room for snubbers

Some boards are frozen. The layout is locked, the copper is poured, the ground plane is a solid sheet, and adding a 0603 snubber means cutting a trace under a BGA. In that box, chasing gate oscillation is academic. You can't fix what you can't touch. The pragmatic transition is to shift the switching frequency or spread-spectrum dither until the ringing falls outside the frame-pacing vulnerability window. Not elegant. But it works.

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The pitfall here is the temptation to reduce gate drive strength instead—slowing the turn-on, raising the switching loss, and still not killing the oscillation because the parasitic inductance dominates. I have watched a group burn three spins on gate resistor values while the real fix was a 1 nF capacitor from the switch node to the power-ground island—except that island didn't exist in the layout. So they lived with the ring. The frame pacing? Acceptable. The thermal budget? Shot. Choose your poison. If the layout is fixed and the snubber footprint is absent, stop optimizing the gate loop. launch optimizing the load transient profile by adding a bulk capacitor at the point of load. That moves the issue outside the GaN's bandwidth—a cheap surrender.

Open Questions and FAQ

Does gate oscillation always cause visible stutter?

Not always—and that ambiguity is what makes this issue so insidious. You can probe a GaN FET rail, see a 50 MHz ring that looks awful on the scope, yet the game plays smooth for hours. I have chased oscillations that existed only at idle, disappearing the moment the GPU actually drew load. The catch is that intermittent stutter—the kind that shows up once every three minutes during a firefight—often traces back to a narrow operating point where the gate driver and the FET’s input capacitance hit a resonance peak. Most groups miss it because they only check at 100% load or 0% load. The real diagnostic gap lives between 20% and 60% duty cycle, especially during frame-slot transitions. So no, visible stutter is not guaranteed. But if you see a lone frame drop that correlates with a power-state change, oscillation should be your second suspect—right after power integrity, which is frequently the same root cause wearing a different hat.

Can firmware fix gate oscillation?

Sometimes, but only if the root cause is a timing or dead-slot mismatch rather than a genuine impedance glitch. I have seen crews apply a firmware patch that adjusted the gate-driver’s slew rate register and the oscillation disappeared—for five days. Then the FET aged, the threshold voltage drifted 20 mV, and the ringing came back worse. Firmware can mask the symptom by shifting the operating point away from the resonant frequency, but it can't fix a PCB layout where the gate loop inductance is too high. That's a geometry snag, not a register snag. One team I worked with spent three weeks tweaking switching speed parameters in firmware, only to revert to a hardware fix—a 1-ohm series gate resistor—that cost five cents and took an hour to validate. The cheap option works. The expensive option is convincing yourself that software can outrun physics. It rarely does.

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“The hardest oscillation to fix is the one you can’t see because the firmware hides it.”

— Senior hardware engineer, after reverting a firmware-only “fix” for the third slot

Is GaN inherently more ringy than Si?

Yes, but not in the way most articles claim. The common narrative—GaN switches faster, so it rings more—is true but oversimplified. What actually matters is the ratio of the gate-loop parasitic inductance to the FET’s input capacitance. GaN FETs typically have lower gate charge and faster edges, which means even a tiny PCB trace inductance can create a resonant tank that silicon would ignore. I have measured a 3 mm gate trace that produced a 120 MHz ring on a GaN device, while the same layout with a silicon MOSFET showed nothing above 30 MHz. That said, GaN is not inherently unstable. It's simply more sensitive to layout geometry that was acceptable in the old regime. The trade-off is brutal: faster switching improves efficiency, but it also lowers the tolerance for parasitic inductance. You can't just drop a GaN FET into a silicon socket and expect clean gate drive. The fix order is clear—shorten the gate loop primary, add series resistance second, and never assume the driver’s internal impedance is low enough.

What’s the cheapest fix that actually works?

A solo surface-mount resistor, 1 to 4.7 ohms, placed directly at the gate pin. No ferrite bead, no active clamping, no layout spin. I have seen this resolve 70% of gate oscillation cases in the opening pass. The catch is that the resistor also slows the switching edge, which increases switching losses—usually by 2–5%, which is acceptable for most gaming hardware if the gain is consistent frame pacing. The anti-pattern is to rely entirely on a ferrite bead, which can create a parallel resonance with the gate capacitance and make the problem worse. That hurts. The cheapest fix is also the most mechanical: verify that the gate-driver output trace is shorter than 10 mm and not routed under any high-frequency inductor. If your layout already violates that, no resistor value will fully fix the ring. You then have two choices: respin the board or accept the stutter. Most units choose the resistor and phase on. Few regret it.

Summary and Next Experiments

Recap the fix order

begin with the gate driver primary. Period. I have watched crews spend three weeks swapping PCB stack-ups while a 10 Ω gate resistor sat on the bench. The order that sticks: reduce gate drive strength, add series resistance at the driver output, then—only then—look at the power loop. The catch is that every extra nanohenry in the gate path shifts the ringing frequency. So keep the resistor physically tucked against the GaN FET gate pin. That sounds fine until you realize the layout forces a 5 mm trace. Then you need a higher resistance value—and that costs you switching speed. Trade-off accepted.

probe: measure gate waveform before and after

Clip a low-inductance scope probe directly across the gate-source pads—not the test point on the schematic, not the via two centimetres away. I have seen engineers measure clean waveforms at the driver output while the FET gate oscillates at 180 MHz. The difference is the trace inductance between them. Run the board at full load, capture the turn-off ring amplitude, then make one change—one—and capture again. Most teams skip this: they fiddle with three components at once and never know which one fixed the frame pacing. Document the peak-to-peak overshoot. If it drops below 2 V, you're safe. If not, keep stepping.

Try: reduce gate drive by one phase

Every GaN driver has a programmable drive strength register or a resistor divider. Drop it one notch. What usually breaks first is the miller plateau—the FET starts conducting during the dead phase because the gate can not charge fast enough. That hurts. You lose efficiency, the output voltage sags, and frame pacing stutters. The trick is to run a 50 mHz load transient test: inject a 10 A move and watch the output voltage settle. If the undershoot exceeds 3 % of nominal, the drive strength is too low. Bump it back up and try the next fix—a 1 Ω gate resistor.

Try: add 1 Ω gate resistor and observe

One single ohm. That's often enough to kill the 200 MHz oscillation without killing the switching edge. Quick reality check—1 Ω adds roughly 1 ns of delay per 1 nF of input capacitance. For a typical GaN FET that's maybe 500 ps. Not a problem. The pitfall is placing the resistor on the wrong side of a via. Place it at the gate pin, series connection, no stub. Measure the rise window before and after. If the rise slot creeps above 5 ns, you have gone too far. Use a smaller value—0.5 Ω, or a ferrite bead rated for 100 MHz and above. Don't use a bulk ferrite; those saturate at 200 mA and you lose all damping.

'We added 1.1 Ω and the frame pacing ripple dropped from 480 µs to 90 µs. The fix took ten minutes. The blame game took two weeks.'

— senior hardware lead, 400 W GaN PSU teardown postmortem

The next experiment: repeat the same scope capture at the GPU load step. Run the benchmark that previously showed stutter—usually a 4K scene with sudden brightness shifts—and log the frame slot histogram. If the 99th percentile frame time drops by more than 2 ms, you nailed it. If not, the oscillation was not the primary cause. Try reducing the power-stage switching frequency by 20 % and re-run the gate waveform test. That moves the noise band away from the controller’s bandwidth. Sometimes the fix is not the gate—it's the control loop. But open with the gate. Always start with the gate.